1. Field of the Invention
This invention relates to phase-locked loop (PLL) devices and, more particularly, to a method for entering a test mode and detecting loop filter leakage within the PLL without using a dedicated test pin.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Phase-locked loops (PLLs) are routinely used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. In some cases, PLLs may be used in the input/output (I/O) interfaces of digital integrated circuits to hide clock distribution delays and to improve overall system timing. Regardless of application, a PLL may generally be used for generating one or more clocking signals, which are in phase and/or frequency alignment with a reference clock signal.
More specifically, a PLL is a closed-loop device that utilizes a voltage-controlled oscillator (VCO) for obtaining accurate phase and frequency alignment between two signals, typically referred to as feedback and reference clock signals. As shown in FIG. 1, conventional PLLs generally include four main components: a phase frequency detector (PFD) 110, a charge (or voltage) pump 120, a loop filter 130 and a voltage controlled oscillator (VCO) 140. In some cases, frequency dividers 150 and/or 160 may be included for dividing the frequencies of the feedback (FVCO) and reference (FREF) clock signals.
During operation of the PLL, the PFD monitors the phase/frequency difference between an externally-provided reference signal and the feedback signal generated by the VCO, and as a result, generates compensating “up” and “down” control signals when the feedback signal lags or leads the reference frequency or phase. The up/down control signals are passed through the charge pump and filter to produce a control voltage (VCTRL) for controlling the VCO. The control voltage drives the VCO (by increasing/decreasing the oscillation frequency therein) to maintain a predetermined phase relationship between the reference and feedback signals. In this manner, the PLL may be ideally configured for generating one or more output signals, which demonstrate a relatively low (and preferably zero) static phase offset from the reference clock signal at the lock point.
As shown in FIG. 1, one of the frequencies (FVCO) output from the VCO may be fed back to the PFD as a feedback signal (FFB). If frequency divider 150 is included, PLL 100 may function as a frequency multiplier. For example, frequency divider 150 may be used to produce the feedback signal (FVCO/N) by dividing the VCO output frequency by an integer value (N). As noted above, however, frequency divider 150 may not be included in all embodiments.
Circuit designers and manufactures constantly strive to improve the accuracy, reliability and quality of PLL devices. One problem affecting all three characteristics is the occurrence of current leakage within the PLL. Many of the components within a PLL contribute to the current leakage problem including, but not limited to, the PFD, charge pump, loop filter and VCO. At some levels, current leakage within the PLL may result in unwanted spurious spectrum, degraded cycle-to-cycle jitter and frequency drift. In the extreme case, current leakage within the PLL may cause system failure and customer-return, a condition that is undesirable for obvious reasons.
Therefore, a production test is needed to screen for current leakage within each PLL device before that device is shipped to a customer. In some cases, a standard standby current test may be used in a post-production phase for detecting current leakage within a PLL. The standby current test is generally conducted with the PLL in a power down test mode and may be used for detecting current leakage within the PFD, charge pump and/or VCO portions of the PLL. The standby current test is generally sensitive to leakage currents within the micro-amp (μA) range.
However, a problem arises when one attempts to measure the amount of current leakage attributed to loop filter 130. Because loop filter leakage is so small (generally on the order of nA), it is usually masked out by leakage from other on-chip circuitry, and therefore, cannot be detected by the standard standby current test.
In the past, circuit designers and manufacturers have opted to either (i) add one or more dedicated test pins and associated test circuitry to the PLL device for detecting loop filter leakage, or (ii) not screen for loop filter leakage and accept the risk of this defect. If a dedicated test pin is added, the circuit designer or manufacturer may perform the loop filter leakage test at the package level or at the wafer level. In some cases, a Serial Data Interface and associated logic (e.g., I2C interface and logic) may be used to enter into such a test.
However, the conventional solutions described above are often undesirable for several reasons. For example, disadvantages of the conventional solutions include: (i) the additional cost of adding one or more dedicated test pins to the package, (ii) the high cost of performing wafer-level testing, and/or (iii) the fact that standard test logic (such as I2C logic) is not always available on all products. In addition, each solution increases the cost of manufacturing, and as such, may be unsuitable for low cost products. Furthermore, most manufacturers would agree that the risk of parts being shipped to customers with this reliability problem is highly undesirable. Therefore, opting out of the loop filter leakage test is usually not considered a viable option.
For at least the reasons set forth above, it would be desirable to have an inexpensive test for loop filter leakage that does not require dedicated test pin(s), wafer-level testing or standard test logic.